1. Field of the Invention
The present invention relates to a spin-on process, and more specifically, to a re-performable spin-on process capable of reducing instances of scrapped semiconductor wafers.
2. Description of the Prior Art
In a multilevel metallization process, metallic conductive layers and low-k dielectric layers connect each of the metal oxide semiconductor (MOS) transistors on a semiconductor wafer to form a stacked circuit structure. Since the multilevel metallization process improves the integration of the semiconductor wafer, it is therefore commonly applied to very large scale integration (VLSI) processes. Additionally, for depositing a void-free dielectric layer with good step coverage ability on the metallic conductive layers, a sandwich-type dielectric structure is always available to the VLSI processes.
Please refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are schematic diagrams for illustrating forming a sandwich-type dielectric structure 22 on a semiconductor wafer 10. As shown in FIG. 1, the semiconductor wafer 10 includes a silicon substrate 12, a plurality of metal interconnecting wires 14, and a silicon dioxide layer 16 formed on the semiconductor wafer 10. Additionally, the silicon dioxide layer 16 is formed through performing a plasma enhanced chemical vapor deposition (PECVD) process. Then, a spin-on process is performed for forming a spin-on glass (SOG) layer 18 on the semiconductor wafer 10, the SOG layer 18 filling trenches 17 in the silicon dioxide layer 16, as shown in FIG. 2. Subsequently, after a curing process is performed on the SOG layer 18, an etching back process is performed for partially removing the SOG layer 18 so as to reduce a thickness of the SOG layer 18, as shown in FIG. 3. Finally, as shown in FIG. 4, a PECVD process is performed for depositing a silicon dioxide layer 20 on the SOG layer 18, thereby completing the fabrication of the sandwich-type dielectric structure 22.
Since the line width of the semiconductor process is gradually shrinking, the width of each metal interconnecting wire 14 gets smaller and smaller. However, for maintaining a low resistance of each metal interconnecting wire 14, a thickness of each metal interconnecting wire 14 cannot be reduced without restriction so that each metal interconnecting wire 14 has a high aspect ratio and a severe topography. Therefore, the SOG layer 18 always has poor thickness uniformity. In addition, after the spin-on process is completed, an edge bevel rinse (EBR) process is usually performed for cleaning an edge of the semiconductor wafer 10, and the EBR process may cause the semiconductor wafer 10 to be contaminated by chemical solutions. Conventionally, when the SOG layer 18 has poor thickness uniformity or is contaminated by chemical solutions, the semiconductor wafer 10 is immediately scrapped, thus wasting resources and increasing production costs.